5th April 2021
CTU SSTC
Introduction
After my success with DRSSTC I my university Czech Technical University in Prague (CTU) asked me to make a very small table top solid state Tesla coil. The only requirements are that it has to fit inside 80x30x30 shelf with practically no air circulation for cooling. The coil will be displayed in PlasmaLab at a faculty of nuclear sciences and physical engineering.
Construction
This project was by far the most frustrating as the coil has to be very small and therefore work at very high frequencies, it's not as easy to work with. I decided to run half-bridge topology driven by a GDT. For a driver i choose UD2.7 board, this was the easiest solution as i had one laying around. The project sounded simple enough, but it was fail after fail. It literally took me many months of work and failures before i gave up on the idea of working with 660kHz and started winding a secondary with smaller diameter wire and a larger topload.
The main issue was that i was not capable of driving the gates properly at higher frequencies. I used at least 4 different GDTs with different sizes and core materials but they all worked poorly at best.
4th August 2021
Unmounted GDT, ferrite core, 10 turns
Nice looking driver output to the primary of the GDT
Secondary of the GDT, absolutely unusable
New secondary coil with new topload, estimated resonance frequency ~400kHz (old 660kHz system in the back)
Solving driver issues
With the new secondary coil and topload I reached new resonant frequency of 391kHz. The problem was not fully solved though, the gate waveforms still looked awful! I have tried 5 different GDT core materials but I only got a small improvement. My only conclusion was that the UD2.7 driver is somehow broken. It seemed to deliver insufficient current to the primary of the GDT. So I decided to make a driver from scratch. I got my inspiration from classic SSTC drivers, with antenna feedback and inverting/non-inverting FET drivers.
Inspiration for the driver came from this schematics from Kaizer Power Electronics:
The idea behind the driver is very straight-forward. Antenna receives feedback from the secondary, C2 capacitor blocks any DC offset which could cause duty cycle asymmetry. D1,D2 diodes are protecting the schmitt-inverters from under and overvoltage. The schmitt-inverters "shape" the feedback sinewave to a clean square-wave which is then fed into the FET drivers. C4 is again a DC blocking cap. UCC37321/2 drivers also have enable pin, so the bridge can be easily interrupted to limit the power or to play audio.
Finally I had some success with this driver, gate-waveforms finally looked promising but a few problems popped out. First of all, even with C2 blocking capacitor, the gate waveforms were far from symmetric. The duty cycle was not 50%, more like 60%:40%. That would have not been that big of a problem but the main thing was, that the feedback was noisy and sometimes it didn't even start to oscillate. The antenna feedback was also very sensitive, I had to place the antenna exactly to a position where the feedback would kick-in.
No more antenna! I switched to a feedback transformer, which partially solved my problems but there was still a big problem left; The feedback picks up all the frequencies around the coil! Sometimes it picked up 50Hz from mains before the coil started to correctly oscillate. This would blow up the transistors with ease. So I decided for yet another approach.
Phase lock loop driver
Phase lock loop is a system which generates an output signal at a certain frequency, but the frequency of this output signal can be forced to change. Phase lock loop (PLL) is basically made of 3 fundamental components: Voltage controlled oscillator (VCO), Phase detector (PD), and low pass filter (LP). The idea behind the circuit is such that the VCO's signal is fed to the phase detector which compares the phases between input signal and VCO's. Phase detector then creates a square wave which's duty cycle is given by the difference between the input and VCO's phase. This square wave is then sent through a low pass filter which "averages" the square wave voltage, giving us DC voltage proportional to the difference of the input and VCO's phases. This DC voltage is then applied to the VCO which changes it's frequency accordingly to lock on the phase of the input signal. This way we have a oscillator which oscillates even without an input signal, but can oscillate at a different frequency when fed with an input signal. In an SSTC driver, we set the VCO's frequency as close as possible to the resonant frequency of the secondary. Then a feedback from the secondary is connected to the input of the PLL. This way the coil can start oscillating at a correct frequency and change it's driving frequency as the secondary resonant frequency also changes thanks to arc and changing environment capacitances.
Again I'm not inventing anything new and so I checked the internet for some nice PLL driver schematic and immeditaly I found the perfect circuit this time from website vn-experimenty.
This driver may look a bit more complicated but it is the same principle as before, only this time we use CD4046 IC for the PLL.
A transformer feedback is utilized again with protective diodes and 74HC14 schmitt-inverters. C6 blocks any DC components from the output of the schmitt-inverters and the input of the 4046 is again protected with clamping diodes. R3 together with C2 make up the low pass filter in the phase lock loop system. Pin 9 (VCOIN) is the VCO's input which sets the oscillating frequency with a DC voltage. PLL will only work in a certain frequency range, that's why the potenciometer R3 is there to set the VCO's operating frequency to the center of it's frequency range. Resistor R1 together with capacitor C1 sets the VCO's frequency and the R1 together with R2 sets the frequency range in which the VCO can oscillate. The output of the 4046 chip is then sent to FET drivers which drive the primary of a GDT.
I found out that the circuit works even better and more reliable when we place another 10n capacitor after the C6 to filter the square wave as CD4046 chip doesn't like sharp edges. Since TC4451/2 do not have enable pins, I have utilized an AND gate fed with output of a simple interrupter and 74HC14 output.
Finally some decent arcs!
At ~120VAC input and 50% duty cycle I've finally managed to achieve some nice ~10cm sparks.
Neat, but a new problem came to life. At higher power levels (duty cycle >80%) the topload got so hot that it melted the plastic which it was made of. I usually make my toploads by 3D printing a toroid with PLA filament which is then fully covered with aluminum tape. The problem with this tape is that its glue is non-conductive and therefore individual layers of the tape are not electrically connected. It's good enough to add capacitance to the circuit but it cannot keep up with conduction losses when running higher duty cycles. Luckily my previous secondary coil had a solid metal topload, but much smaller one.
With the new setup my resonant frequency has been risen to 481kHz. I was scared that the GDT will work poorly again, but after adjusting C1 in the PLL circuit to achieve this new frequency, the GDT waveforms actually looked almost the same as with previous frequency of 390kHz. Sweet! I also used less turns on the primary and adjusted coupling a bit higher for more power.
Unfortunately this project was development on the fly so I haven't even drawn schematics, but the circuit is not much different than the one shown before. Also because of school there was not much time to make any documentation so I only have a few images to share. I'm planning to make a full bridge PLL SSTC which I will fully document. Nevertheless, here are some pictures.
PLL driver board
G-S (red), D-S (yellow) waveforms
Almost finished SSTC in a custom 3D printed case
Finished SSTC running in CW mode (~1kW power draw)
I originally wanted to limit the power with interrupter but then I settled for much easier solution. The coil has 3 modes in which it can operate;
1.) single diode rectification (50Hz operation with no smoothing), 2.) full bridge rectification (100Hz operation with no smoothing), 3.) full bridge rectification and 680uF smoothing capacitor. Power draw in 50Hz mode is roughly 500W, 750W for 100Hz and 1kW for CW mode.
In 50Hz mode the coil can run indefinitely without overheating, I didn't test 100Hz, but I think the coil shouldn't overheat. As for a CW mode, it's a different story. In CW mode the primary coil gets quite hot soon. After 10 minutes it reaches 90C easily. The primary coil is the main limiting factor here, the secondary is a bit "colder" while the transistors are only quite warm. Although when in closed box the transistors reach about 60C after 10minutes CW operation even with 2 fans blowing cold air on the heatsink.
Clean audio
A huge advantage of PLL driving method is that we can modulate the driving frequency very easily by directly coupling an audio signal to the VCO. I have bought a small board containing Bluetooth module receiving an audio signal from a phone and outputting it to the VCO. The output voltage of the Bluetooth module is the same as you would find in a headphone jack (roughly 1Vpk-pk). This voltage is enough to shift the driver's frequency by +-6kHz which is enough to module the power of the coil to playback quite loud but most importantly clean audio. The Bluetooth module is absolutely fantastic for this application, as it also obviously comes with galvanic isolation.
Final specifications
- The coil uses CD4046BE PLL chip to drive half bridge of IRFP460s.
- Coil offers 3 modes of power levels; 50Hz/100Hz/CW with Bluetooth audio connection.
- Resonant frequency of 481kHz. (473kHz with arc).
- Secondary coil is wound with 0.2mm double enamel wire for total of 900 turns.
- Smoothing capacitance in CW mode: 680uF.
- Topload size is roughly 3x11 cm.
- Breakout rod is made out of graphite rod from 9V battery.
Main things I've learnt
- PLL is probably the most reliable method of driving an SSTC.
- There is no need for new super high tech FETs, old IRFP460s are most of the times even more robust anyway.
- Coupling between primary and secondary coil is the main factor when it comes to power draw.
- Always use gate-driver ICs which can be mounted to a heatsink, no DIP packages! They overheat very easily.
- Always short the ground of the driver with the main's earth and lower pole of the secondary.
- Do not use small capacitance in the PLL oscillator circuit as it becomes too sensitive, use at least a few nF if possible.
- Interrupted sparks are always bigger than CW arcs.
- Any small interference in the driving logic can totally mess up the gate-waveforms.
- Design your electronics so that every critical component is easily accessible and replacable.
- Linear voltage regulators are very sensitive to inrush current, use an NTC in the series with the power supply.
- Breakout electrode cannot be made of copper, in CW mode the plasma gets so hot that it immediately melts it.
This project has been a real struggle, but in the end it was well worth it. This project has taught me many things and it has inspired me to create more SSTCs with PLL drive in the future. Actually I'm developing a small SMD PLL driver right now as I'm writing this article.
KiCad 3D model of 8x6 cm PLL SSTC driver with robust FET drivers
Schematics of the PLL driver
And that's not all. This project also inspired me to choose a topic for my bachelor's thesis. I would like to make a fully universal inverter driver with STM32 or FPGA. The driver would be able to drive any FETs/IGBTs, would be able to work in fixed frequency mode and also in PLL mode but with huge frequency range (~1kHz - 1MHz). It would feature over-current, over-temperature, under-voltage and even short circuit detection. This way it should be virtually impossible to destroy the transistors. The driver would also offer galvanic insulation without utilizing GDT. This driver should be able to drive any switch mode power supply, all the way from PC power supplies, lab bench power supplies, induction heaters to high power inverters as Tesla Coils, DRSSTCs etc.
22nd January 2024
Repair
Unfortunately, the coil was damaged during use. I'm not really sure what caused the damage as the report I was given didn't make much of a sense. Well, someone just does not want to get the blame for destroying the coil. But from the looks of it, it seems like the coil simply ran for too long and overheated as the primary coil's insulation wire was melted to the PVC pipe around which it was wound.
Both switching transistors were destroyed. It seemed like an easy fix; a simple replace of the transistors. However after replacing transistors for new ones, the driver itself acted in a weird way. The PLL did not want to lock and after some adjustments to the driving circuit, one of the Gate driving ICs went short circuit. To this day I'm not sure what destroyed the driver IC. Anyway new driver board was needed as the one I used was on a prototyping universal board and it started to be a big mess.
Above I've mentioned developing new driver on a nice PCB which I eventually used for my SSTC II. However I wanted to experiment a bit with feedback phase lag circuit. Up until now, I was not aware that SSTCs can run in ZCS mode and so the coils I've built were quite inefficient. To run an SSTC in ZCS mode a lag to the feedback loop must be introduced.
I've seen a few people use this trick, by placing a delay circuit between pins 4 and 3 of CD4046 IC.
PLL Driver with phase lag circuit by Tefatronix
I've choose to implement the same circuit but directly on the feedback loop (between feedback CT and pin 14 of CD4046). I've also used D flip flop in combination with some AND/OR gates to check for under voltage and over temperature. The D flip flop makes sure the coil does not act upon these lockouts during the switching cycle but only during switching. If the coil is switching in ZCS mode, this should minimalize losses and potential high voltage spike caused by turning transistor off during high primary current.
My implementation of a PLL driver
I have also added some jumpers to bypass the delay circuit if needed and to see which bias voltage works the best for the CD4046 chip. The chip definitely works best with biasing the input voltage with half of its VDD voltage. When connected to 5V or left disconnected, the chip would not lock on the feedback at all.
What came as a surprise to me is that the delay circuit did not work well. I've used a signal generator to see if the phase on its output changes and it did change indeed, however when running with feedback, the driver's switching phase would not change. Luckily I found a solution on Jakub Tejisčák's website, from who I've been originally inspired to choose PLL as a driving method. In his SSTC, the phase is controllable with a potentiometer on pin 12 (R2) of CD4046. I was aware of this solution already, but until now I had no idea how this works. It's hard to image but the center frequency of 4046 which can be set with both R1 and R2 affects the output phase. Therefore I've done the same trick (except I'm using R1 instead of R2 to tune the phase). This has worked very well!
Primary current and bridge output voltage (ZCS mode)
On first glance it might look like the output voltage does not meet with primary coil zero current crossing. However the delay is caused by the bridge transitioning only after the output capacitance of MOSFETs and snubber capacitors are charged. Shifting the phase closer to zero current only makes it work less efficient and much more noisy. With this phase setting the waveforms are nice and clean. On this scope capture, the coil was running at only 100V on DC bus and the primary current reaches 6Arms.
I have also changed the secondary coil and topload, since the old secondary was overheating easily. The new secondary is roughly 800 turns of 0.3mm wire wound around 10cm diameter PVC pipe with length of 18cm.
50Hz single wave rectified mode
50Hz single wave rectified mode
19th February 2024
CW mode at almost full power (75% maximum bus voltage)
Another repair and improvement
After tuning ZCS the coil was running very well, so well that the transistors were not even heating above the threshold where over-temperature lockout would trip. Sooner than transistors got the chance to heat up that much, the primary coil was getting very hot.
I've decided to wind another primary coil in parallel using the same wire just wound as a double coil. This lowers the effective resistance of the primary circuit which will lead to lower primary temperature. However it also increases coupling as the coil now goes physically higher up the secondary coil. The difference between single primary and double parallel primaries were much bigger than what I would expect. The input power of the coil increased by 53%.
50Hz single wave rectified mode with double primary coil
It is quite clear that the sparks got bigger. However now the transistors also got hot and quite fast. After testing, the transistors reached over-temperature lockout threshold (about 60C) in only 1 minute and 28 seconds, running in CW mode at 1150W of power.
Unfortunately this is also a timestamp marking their destruction. The under-voltage and over-temperature lockout circuits had one fatal flaw.
When either of these circuits trip, the Gate drivers are being fed logical LOW state. However because one of the gate drivers is inverting, their outputs will be LOW and HIGH, meaning the primary coil will have full input voltage across it. Thanks to the DC blocking capacitors, this state does not result in short circuit. However it means that the secondaries of the GDT have nowhere to discharge and that will keep one of the transistors in the on state. The charge on the Gates of power transistors will only discharge through the secondary windings themselves. This is very slow, it takes multiple switching cycles before the transistor is finally turned off. I wasn't aware of this sooner, however I captured some very weird waveform while manually triggering UVLO which were a hint that something is wrong:
Primary current and bridge output voltage during UVLO trip
The primary current suddenly appear to float on another sine wave. This was tested at low input voltage (around 80VDC), so the transistors were able to survive this. However at 325VDC an LTSpice simulation has shown that there is over 14kW of peak power loss on one of the switching transistors. No wonder they blew up.
I have solved this issue by modifying the driver PCB once again:
Improved implementation of a PLL driver
Now there is a circuit that uses another winding on the GDT to short out any of the remaining Gate charge to ground. Notice I have switched one of the Gate drivers (IXDN_6XX to IXDD_6XX). This change was necessary as IXDN_6XX version does not use its Enable pin. I have also added resistor R33 which is quite important, it removes any DC voltage from the DC blocking capacitors so this way they have no voltage across them when Enable pulse goes high again.
I have also removed the phase lag circuit as I'm not using it. I'm now waiting for the new PCB to arrive so I can test everything up. I'm quite scared of the power loss on the transistors. As stated above, they reached 60C in only 88s of operation in CW mode. However the fan blowing on the heatsink was not on during this test which gives me a lot of confidence to think that the transistors will be okay. 60C is not even that hot, it would most likely be okay to set the over-temperature lockout threshold higher.